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I. Operating Principle
Regarding the camera, scenes are captured through the lens, generating optical images projected onto the image sensor surface. These light signals are then converted into analogue electrical signals. Following A/D (analogue-to-digital) conversion, they become digital image signals. These are subsequently processed by the digital signal processing chip, transmitted via the IO interface to the CPU for further processing, and finally displayed on the LCD screen.
Hardware Power Supply
1. AVDD
The analogue power supply for the sensor. Primarily powers the internal photosensitive area and the ADC, constituting a sensitive power source. Issues such as water ripple in camera previews or excessive noise during low-light shooting are generally caused by an unclean AVDD supply. Multiple cameras not operating simultaneously may share a single AVDD supply. However, the AVDD for the front camera and the rear main camera must not be shared. While some cameras may share this supply, an LDO reserve design must be implemented, with the reserved LDO prioritised as a backup for the larger pixels. Each camera's AVDD input must incorporate a reserved RC filter network for debugging purposes. AVDD ripple measurements must be taken with the camera module in a pure black environment.
2. IOVDD
Interface power supply. Primarily powers internal I2C and MIPI circuits. The IO power source typically shares a common pull-up source with the corresponding camera's I2C circuit. Consumes minimal power at the microampere level. Less sensitive to noise, with lower impact.
3. AFVDD
Focus motor power supply. In primary smartphone cameras, this voltage line is typically present to enable autofocus functionality. The camera's voice coil motor (VCM) requires a driver IC to achieve focus. Both pins connect to the driver IC, operating within a permanent magnetic field. By modulating the DC current through the motor's coil via the driver IC, the position of the spring-loaded plate is adjusted, thereby driving vertical movement.
Attempting to open or close the rear camera may reveal audible clacking sounds from the moving voice coil motor. Notably, when closing the camera, the sound becomes more pronounced the closer the phone is to the subject, diminishing as distance increases. Below, Xiaobai provides an explanation.
Impact sound upon activation
When first opening the camera after powering on or restarting, the motor drives to its initial position at the very bottom of its effective travel range. If the travel distance is substantial, it may easily collide with the base. To optimise this issue, consider modifying the initialisation position to the midpoint of the travel range.
4. DVDD
DVDD: Supplies power to the digital signals within the camera's internal chip, typically operating at 0.95V-1.2V. Primarily powers internal modules like the ISP, representing the highest power consumption. For a 50MP camera, the typical DVDD current draw is 236.3mA, with the maximum value unknown. Given that the connector pins on the phone's mainboard have a current-carrying capacity of 300mA, this power line is often designed using two pins to ensure safety.
Like other power supplies, it employs an LDO regulator with a PSRR requirement of ≥20dB at 1kHz to 1MHz. Due to the high current demand, the input-output voltage difference must be minimised. As LDOs are linear devices, their input and output currents are nearly identical. A large voltage difference reduces LDO efficiency, causing energy dissipation as heat and contributing to overall device temperature rise. Furthermore, as the LDO's input derives from the system's BUCK converter output—itself supplied by the DC-DC circuit from VBAT—under constant LDO current conditions, identical DC-DC conversion efficiency applies. A higher LDO input voltage necessitates greater current draw from VBAT by the DC-DC circuit, thereby increasing overall system power consumption. (DCDC: Iin * Vbat ≈ 80% = Iout * Uout, where Iin = Iout * Uout / Vbat / 0.8. With Vbat and Iout fixed, a higher Uout results in greater Iin.)
Hardware Signals
1. I2C
The communication protocol between the camera and the BB chip is I2C. The typical data rate is 400K. Multiple cameras operating simultaneously, such as front and rear primary cameras, must not share a single I2C bus. This prevents insufficient I2C bandwidth from reducing the camera's response speed to the host and increasing camera response latency.
2. MCLK
Beyond critical power supplies, a clock signal exists, provided by the BB chip at 24 MHz. This serves as the clock source for the CCM sensor. MCLK is processed by the sensor to generate PCLK, the pixel clock required for data transmission. A ferrite bead is typically series-connected in its path to mitigate RF desense issues.
3. VSYNC
Field synchronisation signal. In dual-camera systems, multiple cameras must expose simultaneously to capture data. Therefore, the VSYNC signals from all cameras are connected together for synchronisation. Cameras operating simultaneously should be isolated with 0R resistors for debugging purposes.
PCB Design
AVDD: Place the RC filter combination near the connector; position the 0.1μF capacitor near the connector, followed by the 4.7μF capacitor. The ground of the capacitor must be connected to the analogue ground (AGND) on the camera module and routed down to the main ground via a via near the connector. If an LDO is reserved, it must also be placed near the connector. AVDD requires protection; routing should be routed with a ground plane. Minimise layer transitions; prohibit routing parallel to or adjacent to current, RF, or clock signals.
DVDD: Capacitors placed near the connector. Due to high current, trace width must meet corresponding current requirements.
IOVDD: Capacitors placed near the connector. Low current; standard trace width suffices.
AFVDD: Same as AVDD. The AFGND pin must connect directly to the negative terminal of its corresponding decoupling capacitor and be positioned near the main ground beneath the socket. It must not have any physical connection to the GND network on other layers.
The trace width for all three power lines is designed based on a 1A current carrying 1mm width.
MIPI: Typically includes series common-mode chokes, though current projects often omit them. Test points for MIPI signal verification must be positioned along the MIPI trace path. Routing should remain on inner layers; avoid top-layer routing except for BB and connector ends. No more than four vias are permitted along the entire path. After layer transitions, maintain a complete reference ground plane. Each MIPI Data and MIPI CLK pair must be individually grounded. Where separate grounding is unfeasible, pairs must adhere to the 3W principle. Differential impedance shall be controlled at 100 ohms ±10%. Differential P and N traces shall be equal in length, maintained at 15 mil, with 40 mil spacing between pairs.
MCLK: Classified as a high-speed signal. Implement robust 3D ground planes. Utilise spring-loaded pins during measurement to ensure waveform integrity. Failure to adequately protect MCLK signals may result in waveform distortion, manifesting as significant defects in performance.
Maintain continuous GND on the top and second layers beneath the connector; no routing permitted.
From a mobile hardware design perspective, camera-related components are relatively limited. The most frequent issues typically involve camera scene power consumption, MIPI signal testing, and significant image quality defects. PCB design plays a crucial role in hardware engineering, where sound design often prevents numerous problems.